PIC32MX3XX/4XX
12.0
I/O PORTS
General purpose I/O pins are the simplest of peripher-
als. They allow the PIC ? MCU to monitor and control
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) of the “PIC32MX Family
Reference Manual” , which is available
from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
sheet for device-specific register and bit
information.
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Following are some of the key features of this module:
? Individual Output Pin Open-drain Enable/Disable
? Individual Input Pin Weak Pull-up Enable/Disable
? Monitor Selective Inputs and Generate Interrupt
when Change in Pin State is Detected
? Operation during CPU Sleep and Idle modes
? Fast Bit Manipulation using CLR, SET and INV
Registers
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
D
Q
SYS CLK
CK
EN Q
ODC
WR ODC
RD TRIS
1
0
I/O Cell
0
1
D
Q
CK
EN Q
TRIS
1
0
WR TRIS
D
Q
Output Multiplexers
WR LAT
CK
EN Q
LAT
I/O Pin
WR PORT
RD LAT
1
RD PORT
Sleep
0
Q
Q
D
CK
Q
Q
D
CK
SYS CLK
Synchronization
Peripheral Input
Peripheral Input Buffer
R
Legend:
Note:
R = Peripheral input buffer types may vary. Refer to Table 1-1 “Pinout I/O Descriptions” for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
? 2010 Microchip Technology Inc.
DS61143G - page 101
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